Understandably, miniaturization is a main objective of many of today's electronic component developers and manufacturers who design and produce semiconductor chips. Today's chips, for example, contain many times the number of connections of chips of only a few years ago, and further miniaturization efforts are ongoing. Accordingly, developers of various electronic packages (e.g., chip carriers) and printed circuit boards or cards intended to accommodate same have been similarly encouraged to provide higher density connections to accommodate these chips.
As is known, semiconductor chips and the corresponding electronic package structures accommodating same utilize extremely small conductive members such as spherically-shaped solder balls or paste, or minute quantities of conductive paste, as the connecting medium between the chip and the structure's hosting substrate, as well as, often, use of such elements to couple the package onto the intended hosting substrate, usually a PCB. Such elements, if solder balls, may possess a diameter of only about three mils (0.003 inch) to about six mils (0.006 inch), and in the final product for incorporation within a larger electronic structure (e.g., a microprocessor), are typically arranged in compact, highly dense arrays (e.g., those with the solder balls positioned apart on only about six mil centers). The electrical circuitry for such packages is also very dense, and may possess line widths as small as about two mils, with two mil spacing between lines. Even smaller elements are presently being contemplated for future products.
It is readily understood that effective interconnection of such chips to the substrates designed to accommodate same as well as between the resulting packages and the corresponding host substrates (e.g., PCBs) are critical to the overall successful operation of the system accommodating same because the failure of even one interconnection may result in system failure, necessitating relatively extensive and expensive repairs to the system as well as a cessation in the functions being performed by the system until such repairs are completed.
Various examples of substrates and substrate products, some of which include electronic packages and/or interposers of one type or another (often for chip testing) are illustrated in the following U.S. patents. The listing of these patents is not an admission that any are prior art to the invention claimed herein.
U.S. Pat. No. 7,511,518 for “Method of Making an Interposer” by Egitto et al. granted Mar. 31, 2009 describes a method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors therebetween. The conductors each electrically couple a respective pair of opposed electrical contacts formed within and protrude from openings also formed within the dielectric layers as part of this method. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semiconductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.
U.S. Pat. No. 7,501,839 for “Interposer and Test Assembly For Testing Electronic Devices” granted Mar. 10, 2009 by Chan et al. describes a test apparatus which uses a pair of substrates and housing to interconnect a host substrate (e.g., PCB) to a semiconductor chip in order to accomplish testing of the chip. The apparatus includes a housing designed for being positioned on the PCB. One of the substrates is oriented therein during device engagement. The engaging contacts of the upper (second) substrate are sculpted to assure effective chip connection.
U.S. Pat. No. 7,292,055 for “Interposer For Use With Test Apparatus” granted Nov. 6, 2007 by Egitto et al. describes an interposer including at least two dielectric layers bonded to each other, sandwiching a plurality of conductors therebetween. The conductors each electrically couple a respective pair of opposed electrical contacts formed within and protruding from openings with the dielectric layers.
U.S. Pat. No. 6,905,589 for “Circuitized Substrate and Method of Making Same” granted Jun. 14, 2005 by Egitto et al. describes a method of making a circuitized substrate in which an electrical common layer is used to form multiple, substantially vertically aligned conductive openings in a multilayered component such as a laminate interposer for coupling a chip to a PCB or the like. The structure, including such a chip and circuit board, is ideally suited for use within an information handling system.
U.S. Pat. No. 6,816,385 for “Compliant Laminate Connector” granted Nov. 9, 2004 by Alcoe describes a flexible shear-compliant laminate connector having a plurality of contacts formed on a first surface and second surface of the connector, wherein select contacts on the first surface are off-set from select contacts on the second surface of the connector. The laminate includes a core comprising copper-invar-copper (CIC), or other similarly used material, such as copper, stainless steel, nickel, iron, molybdenum, etc. The core has a thickness in the range of approximately 1-3 mils. The choice of core material depends upon the material within the chip package being attached thereto. For a ceramic chip package having a relatively low CTE, the overall CTE of the laminate may be about midway between the card and the chip package. According to this patent, this provides improved distribution of stress, and therefore a reduction of stresses within the BGA connections and the interconnection.
U.S. Pat. No. 6,529,022 for “Wafer Testing Interposer for a Conventional Package” granted Mar. 4, 2003 by Pierce describes a wafer testing interposer. The interposer comprises a support having an upper and a lower surface. One or more solder bumps are on the lower surface. One or more first electrical terminals are on the upper surface, substantially corresponding to the position of the solder bumps, and forming a pattern. One or more first electrical pathways pass through the surface of the support and connect the solder bumps to the first electrical terminals. One or more second electrical terminals are on the upper surface of the support. The second electrical terminals are larger in size and pitch than the first electrical terminals, and these are located within the pattern formed by the first electrical terminals. One or more second electrical pathways connect the first electrical pathways to the second electrical pathways.
U.S. Pat. No. 6,516,513 for “Method of Making A CTE Compensated Chip Interposer” granted Feb. 11, 2003 by Milkovich et al. describes a multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy, such as a Teflon/glass particle material formed thereon, with a composite CTE between the CTEs of said first and second layers.
U.S. Pat. No. 6,396,153 for “Circuit Chip Package And Fabrication Method” granted May 28, 2002 by Fillion et al. describes a semiconductor device including a semiconductor substrate, a lower interlayer film formed on an upper side thereof, an intermediate film formed on an upper side thereof, an upper interlayer film formed on an upper side thereof, and a lower plug made of an electrically conductive material that penetrates through the lower interlayer film and the intermediate film. However, the intermediate film has such a material quality that a ratio of an etching rate of the intermediate film to an etching rate of the upper interlayer film is sufficiently small to allow processing of the upper contact hole by etching the upper interlayer film using the intermediate film as a stopper under an etching condition for forming the upper contact hole. This patent further mentions using a polyetherimide adhesive.
U.S. Pat. No. 6,383,005 for “Integrated Circuit Socket With Contact Pad” granted May 7, 2002 by Ho et al. describes an integrated circuit socket having a contact pad. The integrated circuit socket includes a base unit consisting of a base, contact pins and an elastomeric member. The contact pins provide electrical contact for the other elements and the elastomeric member provides the compactness of the assembly. The socket further includes an interposer consisting of a flexible film, a stiffener and a stop layer wherein the contact pad of the flexible film may contact the solder ball of the IC device to buffer the pressure formed by a tight contact when the IC device is moving downward. The socket also consists of an adapter unit and a cover.
U.S. Pat. No. 6,333,563 for “Electrical Interconnection Package And Method Thereof” granted Dec. 25, 2001 by Jackson et al. describes an electrical interconnection package and a method for using same which allegedly increases the fatigue life of a Ball Grid Array (BGA) electrical interconnection. Such BGAs include, understandably, solder balls, the term “ball” standing for solder ball. This structure includes an organic interposer using a high modulus under-fill material to couple an electronic “module.” The organic interposer is then joined to a PCB using standard joining processes. The module can be removed from the organic board at any time by removing the organic interposer using standard rework techniques.
U.S. Pat. No. 6,242,282 for “Circuit Chip Package and Fabrication Method” granted Jun. 5, 2001 by Fillion et al. describes one method for packaging at least one circuit chip including: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on metallized portions of the second side and not on non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.
U.S. Pat. No. 6,239,980 for “Multimodule Interconnect Structure and Process” granted May 29, 2001 by Fillion et al. describes a circuit design logically partitioned into a plurality of blocks. As a first hierarchal assembly level, the blocks are fabricated as individual sub-modules each including at least one electronic component with component connection pads on a top surface, and a first interconnect structure including at least one interconnect layer bonded to the top surfaces, and interconnecting selected ones of the component connection pads. Sub-module connection pads are provided on upper surfaces of the sub-modules. As a second hierarchal assembly level, a second interconnect structure is bonded to the upper surfaces and interconnects selected ones of the sub-module connection pads.
U.S. Pat. No. 6,239,482 for “Integrated Circuit Package Including Window Frame” granted May 29, 2001 by Fillion et al. describes an integrated circuit package including at least one integrated circuit element (chip) coupled to a polymer film, a window frame coupled to the polymer film and surrounding the at least one integrated circuit element, and a quantity of encapsulating material positioned between the at least one integrated circuit element and the window frame.
U.S. Pat. No. 6,156,484 for “Gray Scale Etching For Thin Flexible Interposer” granted Dec. 5, 2000 by Bassous et al. describes a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a fixture for holding the substrate and a mask for single step photolithographic exposure. The result is an array of test probes of pre-selected uniform topography, which make contact at all points to be tested simultaneously and nondestructively. The pad is retained within a dielectric body and includes a “domed” portion and an opposing “sculpted” portion formed using etching, resulting in features having sculpted areas. Both portions are part of an integral structure, such that these are of a single metallic body and arranged in an opposing orientation, one portion being directly opposite the other.
U.S. Pat. No. 5,946,546 for “Chip Burn-In and Test Structure and Method” granted Aug. 31, 1999 by Fillion et al. describes a burn-in frame having at least one window and including resistors having resistor pads is situated on a flexible layer, and at least one integrated circuit chip having chip pads situated in the at least one window. Via openings are formed in the flexible layer to extend to the chip pads and the resistor pads. A pattern of electrical conductors is applied over the flexible layer and extends into the vias. The integrated circuit chip is burned in. The burn-in frame may further include fuses, frame contacts, and voltage bias tracks. After burning in the integrated circuit chip, the chip pads can be electrically isolated and the integrated circuit chip can be tested. This method can also be used to burn-in and test multichip modules.
U.S. Pat. No. 5,880,590 for “Apparatus and Method for Burn-In and Testing of Devices With Solder Bumps or Preforms” granted Mar. 9, 1999 by Desai et al. describes an apparatus for providing temporary connections to a flip-chip style chip having solder bumps or pre-forms protruding therefrom for testing and burn-in while avoiding distortion of the bumps or pre-forms and avoiding wear and damage to a test or burn-in jig such as a ball grid array. The apparatus uses a resilient bucketed interposer which includes recesses with a depth greater than the protrusion of the solder bumps or pre-forms and, preferably, are narrowed at one side to a tear-drop shape. Metallization in the recesses and contacts on the interposer which mate with the jig are preferably textured with dendrites to be self-cleaning. A beveled tongue and groove arrangement translates a slight compressive force to a slight shearing force between the interposer and the chip to ensure good connections to the protruding solder bumps on the chip.
U.S. Pat. No. 5,528,159 for “Method and Apparatus for Testing Integrated Circuit Chips” granted Jun. 18, 1996 by Charlton et al. describes a method and apparatus for testing semi-conductor chips. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relatively loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts.
U.S. Pat. No. 5,353,498 for “Method for Fabricating an Integrated Circuit Module” granted Oct. 11, 1994 by Fillion et al. describes substrate material molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the back side of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the back sides of the chips before the substrate molding material is added to enhance repair.
When providing high density interconnections between a chip or plurality of chips and its hosting electronic package substrate utilizing extremely fine interconnecting elements such as the above-described solder balls or paste quantities arranged in a very dense array, it is quickly understood that precise alignment between chip(s) and substrate is critical. It is further known that the subsequent connection between this hosting substrate (now an interposer) and the hosting, larger PCB substrate, is also critical. The methodologies used to accomplish such interconnections must be precise, in terms of positional accuracy, as well as in temperatures and accommodating external atmosphere environments. Further, such procedures must be adaptable to mass production to thus assure competitive cost savings.
In addition to the foregoing alignment factor, it is also imperative that the structures formed must be as small and compact as possible, to satisfy the aforementioned miniaturization requirements for many of today's products. It is thus imperative that if an electronic package is to be utilized in many of today's demanding products, it must be relatively small, capable of providing several high density connections, and able to be manufactured on a mass production scale.
It is believed, therefore, that an electronic package having the new and unique features defined herein and thus capable of providing high density interconnections between the chip or chips mounted thereon to a larger hosting substrate such as a PCB in a facile yet secure manner, while assuring such connections will remain intact during the life of the system utilizing the resulting assembly, will constitute a significant advancement in the art. It is further believed that methods of making such a package structure as well as larger assemblies incorporating same as part thereof in a facile, relatively inexpensive manner will also constitute significant art advancements.